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agilent HFCT-5915E mt-rj duplex single mode transceiver data sheet description the HFCT-5915E transceiver is a high performance, cost effective module for serial optical data communications applications specified for a signal rate of 155 mbd. it is designed to provide a sonet/sdh compliant link for 155 mb/s long reach links. the HFCT-5915E includes a nose shield and is recommended for optimum emi performance in a complete system. the hfct-5915 does not include a nose shield and is not recommended due to the potential degradation of emi performance in a complete system. the hfct-5915 is available on the rare occasion that a system mechanical design may not allow for a nose shield. features ? mt-rj duplex single mode transceiver long reach sonet oc3 sdh stm1 (l1.1) compliant single +3.3 v power supply multisourced 2 x 5 pin configuration interchangeable with led multisourced 2 x 5 transceivers unconditionally eyesafe laser iec 825/cdrh class 1 compliant temperature range: 0c to +70c applications sonet/sdh equipment interconnect atm 155 mb/s links this module is designed for single mode fiber and operates at a nominal wavelength of 1300 nm. it incorporates agilent?s high performance, reliable, long wavelength optical devices and proven circuit technology to give long life and consistent service. the transmitter section uses an advanced smqw fabry perot laser with full iec 825 and cdrh class i eye safety. the receiver section uses a movpe grown planar pin photo- detector for low dark current and excellent responsivity. a pseudo-ecl logic interface simplifies integration into a system.
2 pin descriptions pin 1 receiver signal ground v ee rx: 1 directly connect this pin to the receiver ground plane. pin 2 receiver power supply v cc rx: provide +3.3 v dc via the recommended receiver power supply filter circuit. locate the power supply filter circuit as close as possible to the v cc rx pin. pin 3 signal detect sd: normal optical input levels to the receiver result in a logic ? 1 ? output. low optical input levels to the receiver result in a fault condition indicated by a logic ? 0 ? output. this signal detect output can be used to drive a pecl input on an upstream circuit, such as signal detect input or loss of signal-bar. pin 4 receiver data out bar rd-: no internal terminations are provided. see recommended circuit schematic. pin 5 receiver data out rd+: no internal terminations are provided. see recommended circuit schematic. pin 6 transmitter power supply v cc tx: provide +3.3 v dc via the recommended transmitter power supply filter circuit. locate the power supply filter circuit as close as possible to the v cc tx pin. pin 7 transmitter signal ground v ee tx: directly connect this pin to the transmitter ground plane. pin 8 transmitter disable t dis : optional feature for laser based products only. for laser based products connect this pin to +3.3 v ttl logic high ? 1 ? to disable module. to enable module connect to ttl logic low ? 0 ? . the module will be enabled when pin 8 is connected to ttl logic low ? 0 ? , or open circuit. pin 9 transmitter data in td+: no internal terminations are provided. see recommended circuit schematic. pin 10 transmitter data in bar td-: no internal terminations are provided. see recommended circuit schematic. mounting studs/solder posts the two mounting studs are provided for transceiver mechanical attachment to the circuit board. it is recommended that the holes in the circuit board be connected to chassis ground. package grounding tabs connect four package grounding tabs to signal ground. connection diagram note: 1. the transmitter and receiver v ee connections are commoned within the module. t ransmitter data in bar transmitter data in transmitter disable transmitter signal ground transmitter power supply rx tx f f f f f 1 2 3 4 5 f f f f f 10 9 8 7 6 receiver signal ground receiver power supply signal detect receiver data out bar receiver data out top view mounting studs/ solder posts package grounding tabs
3 functional description receiver section design the receiver section contains an ingaas/inp photo detector and a preamplifier mounted in an optical subassembly. this optical subassembly is coupled to a postamp/decision circuit on a separate circuit board. the postamplifier is ac coupled to the preamplifier as illustrated in figure 1. the coupling capacitors are large enough to pass the sonet/sdh test pattern at 155 mbd without significant distortion or performance penalty. if a lower signal rate, or a code which has significantly more low frequency content is used, sensitivity, jitter and pulse distortion could be degraded. figure 1 also shows a filter network which limits the bandwidth of the preamp output signal. the filter is designed to bandlimit the preamp output noise and thus improve the receiver sensitivity. these components will also reduce the sensitivity of the receiver as the signal bit rate is increased above 155 mbd. noise immunity the receiver includes internal circuit components to filter power supply noise. under some conditions of emi and power supply noise, external power supply filtering may be necessary. if receiver sensitivity is found to be degraded by power supply noise, the filter network illustrated in figure 3 may be used to improve performance. the values of the filter components are general recommendations and may be changed to suit a particular system environment. shielded inductors are recommended. terminating the outputs the pecl data outputs of the receiver may be terminated with the standard thevenin-equivalent 50 ohm to v cc - 2 v termination. other standard pecl terminating techniques may be used. the two outputs of the receiver should be terminated with identical load circuits to avoid unnecessarily large ac current in v cc . if the outputs are loaded identically the ac current is minimized. the sd output of the receiver is pecl logic and must be loaded if it is to be used. the signal detect circuit is much slower that the data path, so the ac noise generated by an asymmetrical load is negligible. power consumption may be reduced by using a higher than normal load impedance for the sd output. transmission line effects are not generally a problem as the switching rate is slow. the signal detect circuit the signal detect circuit works by sensing the peak level of the received signal and comparing this level to a reference. figure 1. receiver block diagram trans- impedance pre- amplifier filter gnd limiting amplifier pecl output buffer pecl output buffer data out signal detect circuit sd data out
4 functional description transmitter section design the transmitter section uses a buried heterostructure fabry perot laser as its optical source. the package of this laser is designed to allow repeatable coupling into single mode fiber. in addition, this package has been designed to be compliant with iec 825 class 1 and cdrh class i eye safety requirements. the optical output is controlled by a custom ic which detects the laser output via the monitor photodiode. this ic provides both dc and ac current drive to the laser to ensure correct modulation, eye diagram and extinction ratio over temperature, supply voltage and life. solder and wash process compatibility the transceivers are delivered with protective process plugs inserted into the mt-rj connector receptacle. this process plug protects the optical subassemblies during wave solder and aqueous wash processing and acts as a dust cover during shipping. these transceivers are compatible with either industry standard wave or hand solder processes. each process plug can only be used once during processing, although with subsequent use, it can be used as a dust cover. figure 2. simplified transmitter schematic data data pecl input laser modulator laser bias driver laser bias control laser photodiode (rear facet monitor)
5 interface and termination recommendations figure 3 shows one potential +3.3 v coupling scheme. alternative termination techniques are referenced in the design support materials section of this report. also present are power supply filtering arrangements which comply with the recommendations of the small form factor multisource agreement. such a compliance ensures noise rejection compatibility between transceivers from various vendors. figure 3. +3.3 v transceiver interface with +3.3 v lvpecl device f v ee r x f v cc r x f sd f rd- f rd+ z = 50 w z = 50 w terminate at transceiver inputs z = 50 w z = 50 w 10 9 8 7 6 sd lvpecl v cc (+3.3 v) terminate at device inputs lvpecl v cc (+3.3 v) phy device td+ td- rd+ rd- v cc (+3.3 v) 82 w 130 w z = 50 w 1 2 3 4 5 td- f td+ f n/c f v ee t x f v cc t x f 1 h c2 1 h c1 c3 10 f v cc (+3.3 v) t x r x note: c1 = c2 = c3 = 10 nf or 100 nf 100 w 100 w 130 w 130 w 130 w 130 w
6 regulatory compliance feature test method targeted performance electrostatic discharge (esd) to the electrical pins mil-std-883c method 3015.4 meets class 1 (0 to 2000 volts). electrostatic discharge (esd) to the duplex mt-rj receptacle variation of iec 801-2 products of this type, typically, withstand at least 25 kv without damage when the duplex mt-rj connector receptacle is contacted by a human body model probe. electromagnetic interference (emi) fcc class b cenelec en55022 class b (cispr 22a) vcci class 1 transceivers typically provide 12 db margin to the noted standard limits when tested at a certified test range with the transceiver mounted to a circuit card without a chassis enclosure. three transceivers typically provide 20 db of margin in a ?perfect? closed box with the recommended port openings. immunity variation of iec 801-3 typically show no measurable effect from a 10 v/m field swept from 10 to 1000 mhz applied to the transceiver when mounted to a circuit card without a chassis enclosure. eye safety fda cdrh 21-cfr 1040 class 1 accession number: 9521220-29 iec 825 issue 1 1993:11 class 1 cenelec en60825 class 1 tuv certification: 933/510009/01
7 performance specifications absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. it should not be assumed that limiting values of mo re than one parameter can be applied to the product at the same time. exposure to the absolute maximum ratings for extended periods can adv ersely affect device reliability. operating environment transmitter section (ambient operating temperature v cc = 3.1 v to 3.5 v) notes: 1. ambient operating temperature with 2 m/s airflow. 2. outputs terminated with 50 to v cc ? 2v are the thevenin equivalent. 3. the power supply current varies with temperature. maximum current is specified at v cc = maximum @ maximum temperature (not including terminations) and end of life. 4. output power is power coupled into a single mode fiber. 5. 10% - 90% values 6. these inputs are compatible with 10 k, 10 kh, and 100 k ecl and lvpecl inputs. parameter symbol minimum typical maximum units notes storage temperature t s -40 +85 c lead soldering temperature/time t sold /t sold +260/10 c/s output current(other outputs) i o 030ma data input voltage v i gnd v cc v power supply voltage v cc 03.6v parameter symbol minimum typical maximum units notes ambient operating temperature t a 0+70 c1 power supply voltage v cc 3.1 3.5 v data input voltage - low v il - v cc -1.810 -1.475 v data input voltage - high v ih - v cc -1.165 -0.880 v data and signal detect output load r l 50 w 2 parameter symbol minimum typical maximum units notes supply current i cc 50 140 ma 3 power dissipation p diss 0.175 0.42 w optical output power p o -5 0 dbm avg. 4 center wavelength l c 1285 1335 nm spectral width dl -4nm extinction ratio e r 10 - db output optical eye compliant with eye mask bellcore tr-nwt-000253 and itu recommendation g.957 optical rise time t r -2ns5 optical fall time t f -2ns5 data input current - low i il -200 - a data input current - high i ih -200a data input voltage - low v il - v cc -1.810 -1.475 v 6 data input voltage - high v ih - v cc -1.165 -0.880 v 6
8 receiver section (ambient operating temperature v cc = 3.1 v to 3.5 v) notes: 7. this does not include the output load current. 8. this does not include the output load power. 9. minimum sensitivity and saturation levels for a 2 23 -1 prbs with 72 ones and 72 zeros inserted. (ccitt recommendation g.958) 10. these outputs are compatible with 10 k, 10 kh and 100 k ecl and pecl outputs. 11. between 20 hz and 2000 khz with the recommended power supply filter. no degradation above the maximum ? receiver sensitivity at eye center ? specification of ? 34.8 dbm. parameter symbol minimum typical maximum units notes supply current i cc 75 100 ma 7 power dissipation p diss 0.263 0.35 w 8 receiver sensitivity at eye center p in min. (c) -34.8 dbm avg. 9 receiver sensitivity at window edge p in min. (w) -34 dbm avg. 9 maximum input optical power p in max. -8 - dbm avg. 9 operating wavelength l 1280 1335 nm data output voltage - low v ol - v cc -1.840 -1.620 v 10 data output voltage - high v oh - v cc -1.045 -0.880 v 10 signal detect output voltage - low v ol - v cc -1.840 -1.620 v 10 signal detect output voltage - high v oh - v cc -1.045 -0.880 v 10 signal detect - asserted p a p d + 1.5 db -37 dbm avg. signal detect - deasserted p d -45 dbm avg. signal detect - hysteresis p a - p d 0.5 4.0 db signal detect assert time (off to on) as_max 0 100 s signal detect deassert time (on to off) ans_max 0 350 s power supply noise rejection psnr 50 mv p-p 11
9 figure 4. HFCT-5915E package outline drawing pin 1 top view 7.11 (0.28) 4.57 (0.18) 10.0 (0.394) max. 13.59 (0.535) max. 12.4 (0.488) 7.59 (0.299) 17.778 (0.7) 1.778 (0.07) 7.112 (0.28) ? 0.61 (0.024) +0 ? 0.2 (+000) ( ? 008) 10.16 (0.4) 13.97 (0.55) min. front view 4.5 0.2 (0.177 0.008) (pcb to optics center line) 5.15 (0.20) (pcb to overall receptacle center line) dimensions in millimeters (inches) notes: 1. this page describes the maximum package outline, mounting studs, pins and their relationships to each other. 2. toleranced to accommodate round or rectangular leads. 3. the 10 i/o pins, 2 solder posts and 4 package grounding tabs are to be treated as a single pattern. (see figure 6 pcb layout). 4. the mt-rj has a 750 m fiber spacing. 5. the mt-rj alignment pins are in the module. 6. see mt-rj transceiver pin out diagram for details. side view full radius 49.56 (1.951) 9.8 (0.386) max. 9.3 (0.366) max. ? 1.07 (0.042) 3.3 (0.13) 1 (0.039) 0.25 (0.01) 37.56 (1.479) max.
10 figure 5. hfct-5915 package outline drawing pin 1 top view 7.11 (0.28) 4.57 (0.18) 9.6 (0.378) max. 13.59 (0.535) max. 12 (0.472) 7.59 (0.299) 17.778 (0.7) 1.778 (0.07) 7.112 (0.28) ? 0.61 (0.024) +0 ? 0.2 (+000) ( ? 008) 10.16 (0.4) 13.97 (0.55) min. front view 4.5 0.2 (0.177 0.008) (pcb to optics center line) 5.15 (0.20) (pcb to overall receptacle center line) dimensions in millimeters (inches) notes: 1. this page describes the maximum package outline, mounting studs, pins and their relationships to each other. 2. toleranced to accommodate round or rectangular leads. 3. the 10 i/o pins, 2 solder posts and 4 package grounding tabs are to be treated as a single pattern, see figure 8. 4. the mt-rj has a 750 m fiber spacing. 5. the mt-rj alignment pins are in the module. 6. see mt-rj transceiver pin out diagram for details. side view full radius 49.56 (1.951) 9.8 (0.386) max. 9.3 (0.366) max. ? 1.07 (0.042) 3.3 (0.13) 1 (0.039) 0.25 (0.01) 37.56 (1.479) max.
11 figure 6. recommended board layout hole pattern board layout - decoupling circuit and ground planes it is important to take care in the layout of your circuit board to achieve optimum performance from these transceivers. figure 3 provides a good example of a schematic for a power supply decoupling circuit that works well with these parts. it is further recommended that a continuous ground plane be provided in the circuit board directly under the transceiver to provide a low inductance ground for signal return current. this recommen- dation is in keeping with good high frequency board layout practices. board layout - hole pattern the agilent transceiver complies with the circuit board ? common transceiver footprint ? hole pattern defined in the original multisource announcement which defined the 2 x 5 package style. this drawing is reproduced in figure 6 with the addition of ansi y14.5m compliant dimensioning to be used as a guide in the mechanical layout of your circuit board. figure 7 shows the front panel dimensions associated with such a layout. dimensions in millimeters (inches) notes: 1. this figure describes the recommended circuit board layout for the mt-rj transceiver placed at .550 spacing. 2. the hatched areas are keep-out areas reserved for housing standoffs. no metal traces or ground connection in keep-out areas. 3. 2 x 5 transceiver module requires 16 pcb holes (10 i/o pins, 2 solder posts and 4 package grounding tabs). package grounding tabs should be connected to signal ground. 4. the solder posts should be soldered to chassis ground for mechanical integrity and to ensure footprint compatibility with other sff transceivers. spacing of front housing leads holes holes for housing leads 13.34 (0.525) keep out area for port plug 7.59 (0.299) 3 (0.118) 3 (0.118) 6 (0.236) 4.57 (0.18) 17.78 (0.7) 27 (1.063) 1.778 (0.07) 7.112 (0.28) ? 0.81 0.1 (0.032 0.004) 3.08 (0.121) ? 2.29 (0.09) 7.11 (0.28) 9.59 (0.378) 3.08 (0.121) ? 1.4 0.1 (0.055 0.004) ? 1.4 0.1 (0.055 0.004) ? 1.4 0.1 (0.055 0.004) 10.16 (0.4) 13.97 (0.55) min. 3.56 (0.14) 7 (0.276) 10.8 (0.425) 2 (0.079)
ordering information HFCT-5915E model name: HFCT-5915E - preferred option with nose shield fitted hfct-5915 e - non-preferred option without nose shield handling precautions 1. the HFCT-5915E can be damaged by current surges or overvoltage. power supply transient precautions should be taken. 2. normal handling precautions for electrostatic sensitive devices should be taken. figure 7. recommended panel mounting design support materials further technical details and supporting information regarding small form factor transceivers are contained in application note 1189 aimed at providing useful information to the fiber-optic system designer. this document describes pc board layout techniques, alternative termination schemes, power supply filtering, emi considerations and interfacing options. additional performance data is presented in the characterization report and the reliability data sheet. please contact your agilent representative for further information if required. dimensions in millimeters (inches) note: nose shield should be connected to chassis ground. 10.8 0.1 (0.425 0.004) 13.97 (0.55) min. 0.25 0.1 (0.01 0.004) (top of pcb to bottom of opening) 9.8 0.1 (0.386 0.004) 14.79 (0.589) 1 (0.039) 3.8 (0.15) class 1 laser product: this product conforms to the applicable requirements of 21 cfr 1040 at the date of manufacture date of manufacture: agilent technologies inc., depot road, singapore www.semiconductor.agilent.com data subject to change. copyright ? 2000 agilent technologies, inc. 5980-1537e (06/00)

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